1. Field of the Invention
The present invention relates generally to manufacturing processes requiring lithography and, more particularly, to monitoring of lithographic and etch process conditions used in microelectronics manufacturing which is particularly useful for monitoring pattern features with dimensions on the order of less than 0.5 micron.
2. Description of Related Art
Control of a lithographic imaging process requires the optimization of exposure and focus conditions in lithographic processing of product wafers. Likewise, it is also important to optimize etching and other parameters on product wafers. The current solution to the above problems entails the collection and analysis of critical dimension measurements using SEM metrology on multiple pattern types at multiple locations within the chip, and from chip-to-chip. This method is slow, expensive and error-prone. It usually requires the exposure of multiple focus-exposure and etching matrices on product wafers.
Generally, because of the variations in exposure and focus, patterns developed by lithographic processes must be continually monitored or measured to determine if the dimensions of the patterns are within acceptable range. The importance of such monitoring increases considerably as the resolution limit, which is usually defined as minimum features size resolvable, of the lithographic process is approached. The patterns being developed in semiconductor technology are generally in the shape of lines both straight and with bends, having a length dimension equal to and multiple times the width dimension. The width dimension, which by definition is the smaller dimension, is of the order of 0.1 micron to greater than 1 micron in the current leading semiconductor technology. Because the width dimension is the minimum dimension of the patterns, it is the width dimension that challenges the resolution limits of the lithographic process. In this regard, because width is the minimum and most challenging dimension to develop, it is the width dimension that is conventionally monitored to assess performance of the lithographic process. The term "bias" is used to describe the change in a dimension of a feature from its nominal value. Usually the bias of interest is the change in the smallest of the dimensions of a given feature. Further, the term "bias" is invariably used in conjunction with a process such as resist imaging, etching, developing etc. and described by terms such as image bias, etch bias, print bias etc.
Monitoring of pattern features and measurement of its dimensions (metrology) is typically performed using either a scanning electron microscope (SEM) or an optical tool. Current practice in the semiconductor industry is to use topdown SEMs for the in-line metrology of all critical dimensions below approximately 0.7 um. Unfortunately, SEM metrology is expensive to implement, relatively slow in operation and difficult to automate. At best, algorithms that attempt to determine the absolute dimensions at a fixed pattern height (e.g., the interface of the pattern with the underlying substrate), are accurate to only 30-50 nm--a substantial fraction, if not all, of current critical dimension tolerance. The need to measure individual features below 0.25 um poses a serious challenge not just to their imaging capability, but to all the subsystems required for automated measurement--pattern recognition, gate placement, edge detection, and the like.
Although optical metrology overcomes the above drawbacks associated with SEM and AFM metrology, optical metrology systems are unable to resolve adequately for measurement of feature dimensions of less than about 1 micron. Additionally, false sensitivity has limited the applicability of optical microscopy to sub-micron metrology on semiconductor product wafers.
The degradation of optical resolution as chip dimensions approach the wavelength of light precludes the application of optical microscopy to the measurement of individual chip features. Even setting aside the accuracy requirement for in-line metrology, the blurred images of adjacent edges overlap and interfere, and the behavior of the intensity profile of the image no longer bears any consistent relationship to the actual feature on the wafer. It is this loss of measurement "consistency" (definable as a combination of precision and sensitivity) that establishes the practical limit of conventional optical metrology in the range of 0.5-1.0 um.
With regard to false sensitivity, the thin films used in semiconductor manufacturing vary widely in their optical characteristics. Optical metrology is susceptible to variations in the thickness, index of refraction, granularity and uniformity of both the patterned layer and underlying layers. Film variations that affect the optical image can be falsely interpreted as variations in the pattern dimension.
Improvements in monitoring bias in lithographic and etch processes used in microelectronics manufacturing have been disclosed in U.S. patent application Ser. Nos. 08/359,797, 08/560,720 and 08/560,851. In Ser. No. 08/560,851, a method of monitoring features on a target using an image shortening phenomenon was disclosed. In Ser. No. 08/560,720, targets and measurement methods using verniers were disclosed to measure bias and overlay error. In these applications, the targets comprised arrays of spaced, parallel elements having a length and a width, with the ends of the elements forming the edges of the array. While the targets and measurement methods of these applications are exceedingly useful, they rely on the increased sensitivity to process variation provided by image shortening.
Accordingly, there is still a need for a method of monitoring pattern features of arbitrary shape with dimensions on the order of less than 0.5 micron, and which is inexpensive to implement, fast in operation and simple to automate. There is a need for a process for determining bias which enables in-line lithography/etch control using optical metrology, and wherein SEM and/or AFM metrology is required only for calibration purposes.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a measurement tool, test pattern and evaluation method for determining exposure and focus conditions whereby one pattern group is capable of distinguishing between exposure and focus problems in semiconductor pattern processing.
It is another object of the present invention to provide a measurement tool, test pattern and evaluation method for determining etching time and rate conditions and other etching process conditions whereby one pattern group is capable of distinguishing between etching time and rate problems and other etching process problems in semiconductor pattern processing.
A further object of the invention is to provide a method of evaluating focus-exposure and etching parameters which may be used with existing metrology instruments and exposure and etching equipment.
It is yet another object of the present invention to provide a method of evaluating focus-exposure and etching parameters which is easy and inexpensive to utilize.
It is also an object of the present invention to provide a method and target for determining bias and overlay error in patterns deposited as a result of lithographic processes.
It is a further object of the present invention to provide a method and target which combines measurement of bias and overlay error in deposited patterns, and which utilize little space on a wafer substrate.
It is a further object of the present invention to provide a process for measuring bias using targets which are intentionally not resolved by the metrology tool employed.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.